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  high speed, 200 db range, logarithmic converter data sheet ADL5304 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features optimized for very fast response at all input currents overall bandwidth of >4 mhz for inputs >1 a bandwidth: 25 khz at input of 1 na and 350 khz at 10 na 10 decades of input range: 1 pa to 10 ma law conformance: 0.25 db from 100 pa to 100 a log ratio or fixed-intercept operation precision voltage references and reference current adaptive photodiode (pd) bias for low dark current programmable log slope and intercept default log slope of 10 mv/db at vlog pin single- or dual-supply operation applications high accuracy optical power measurement wide range baseband log compression versatile detector for high speed apc loops general description the ADL5304 is a high speed logarithmic converter with fast response and low noise over a 200 db (1 pa to 10 ma) measure- ment range. the ADL5304 provides a nominal logarithmic slope of 10 mv/db (200 mv/decade); other values are easily configured. logarithmic intercept can be programmed over a wide range with the internal 100 na current source or externally for log ratio applications. the default intercept value of 3.162 fa places the midpoint of the measurement range of 100 na at v log = 1.5 v. a single positive supply of 5 v is all that is required for operation over a specified 1 pa to 3 ma input range. dual-supply operation extends the specified input current range to 10 ma. the ADL5304 accepts two current inputs to the logarithmic argument. the numerator input, i num , flows in the collector of an npn transistor, connected in a feedback path around a low offset jfet amplifier. the denominator current, i den , is treated in the same way, which allows for log ratio operation. the input summing nodes (inum and iden) operate at a constant default voltage of 1.5 v. the vsm1 to vsm4 pins flank the inum and iden inputs to provide a guard voltage to minimize leakage currents. adaptive photodiode biasing is provided for optical measurements. a monitor current 1.1 times i num is output at the imon pin, and an external resistor, r mntr , at 10 times the photodiode series resistance (r s ) applies a voltage across the photodiode that 1st order keeps the internal pd junction at 0 v to minimize dark current. the vlog output is buffered and can be rescaled through internal gain setting resistors. the internal i log varies from ?400 a to +400 a as i num changes over 10 decades from 1 pa to 10 ma. this corresponds to 0.5 v to 2.5 v at the vlog pin in the default configuration shown in figure 1 . accurate 1.5 v (pin 1p5v) and 2.0 v (pin 2vlt) reference outputs allow precise repositioning of the intercept using external resistors. the ADL5304 is available in a 32-lead, 5 mm 5 mm lfcsp and specified for operation from ?40c to +85c. simplified block diagram ADL5304 09459-001 2 30 3 4 5 6 8 7 monitor and pd bias (1.1 i num ) temperature compensation 1.5v 1.5v 32 31 26 9 imon vnum innm vden hfcp comm nmfs vneg dnfs v neg indn 1p5v 2vlt dcbi bsdc vsm1 vsm2 vsm3 iref iden inum vsm4 10 11 27 29 28 100na 1.5v 17 24 2v bias and v ref 12 13 14 acom 15 16 inps inms vlog 23 22 5k ? 5k? 1k ? 1k ? 7.5k ? 21 20 19 18 scl1 scl2 scl3 acom r mntr vpos v num v den i log figure 1.
ADL5304 data sheet rev. 0 | page 2 of 32 table of contents features .............................................................................................. 1 ? applications....................................................................................... 1 ? general description ......................................................................... 1 ? simplified block diagram ............................................................... 1 ? revision history ............................................................................... 2 ? specifications..................................................................................... 3 ? absolute maximum ratings............................................................ 5 ? esd caution.................................................................................. 5 ? pin configuration and function descriptions............................. 6 ? typical performance characteristics ............................................. 7 ? test circuits..................................................................................... 13 ? terminology .................................................................................... 16 ? theory of operation ...................................................................... 17 ? basic concepts............................................................................ 17 ? optical measurements............................................................... 17 ? circuit description .................................................................... 18 ? applications information .............................................................. 25 ? using the ADL5304.................................................................... 25 ? using a negative supply ............................................................ 26 ? evaluation board schematic and silkscreens ............................. 27 ? outline dimensions ....................................................................... 29 ? ordering guide .......................................................................... 29 ? revision history 9/11revision 0: initial version
data sheet ADL5304 rev. 0 | page 3 of 32 specifications v pos = 5 v, v neg = 0 v, t a = 25c; iden = iref; vsm1 to vsm4, 1p5v, dcbi, and inps tied together; scl1 = vlog; scl2 = inms; scl3 = open; scale = 200 mv/dec; vlog output load r l > 2 k, unless otherwise noted. upper case indicates a pin name (for example, vlog) and subscripted indicates signal name (for example, v log ). table 1. parameter test conditions/comments min typ max unit input interfaces inum, iden, vsmx pins specified current range flows toward each input pin (inum and iden), ?5 v v neg ?2 v 1 ?12 10 ?3 a v neg = 0 v 1 ?12 3 ?3 a temperature drift (inum and iden) ?40c < t a < +85c 0.01 mv/c input guard offset voltage v inum ? v vsum ?2 0.6 +2 mv logarithmic output vlog pin, referenced to acom; input applied to inum 1 logarithmic slope, v y 25c 195 200 205 mv/dec ?40c < t a < +85c ?2 +3 mv/dec logarithmic intercept, i z 2 extrapolated input current at vlog = 0 v 3.162 fa logarithmic offset difference between v log and v sum with i num = i den ?8 +5 mv ?40c < t a < +85c 25 v/c logarithmic law conformance error maximum deviation from best fit over 1 na to 100 a range ?0.7 0.2 +0.7 db vlog output inps, inms, vlog, scl1, scl2, scl3 pins output buffer offset voltage ?3 +0.1 +3 mv output buffer bias current flowing out of the inps pin ?1.3 a incremental input resistance pin inps 12 m output range r l open vneg + 0.2 vpos ? 0.2 v output noise spectral density 3 i num > 1 na <6 v/hz small signal bandwidth i num = 1 na 25 khz i num = 10 na 350 khz i num = 100 na 1.2 mhz i num > 1 a 4 mhz falling edge settling times 4 i num = 100 na to 10 na 10 s i num = 1 a to 100 na 2.2 s i num = 10 a to 1 a 0.5 s i num > 10 a <0.5 s nominal voltage swing for input current range of 1 pa to 10 ma 0.5 2.5 v output impedance frequency < 1 mhz <2 reference outputs 1p5v, 2vlt, iref pins 1p5v (referenced to acom) 25c 1.495 1.500 1.505 v ?40c < t a < +85c 30 v/c output current ?10 +5 ma 2vlt (referenced to acom) 25c 1.995 2.000 2.005 v ?40c < t a < +85c 31 v/c output current sourcing only 0 20 ma iref 5 25c 100 na ?40c < t a < +85c ?70 pa/c photodiode bias imon pin; i mon = 1.1 i num midrange value at a photodiode current = i num = 100 na 110 na maximum value at i num = 1 ma (r s 100 ), r mntr = 10 r s (r s = photodiode series resistance) 10.5 11 11.5 ma imon compliance 0 3.0 v
ADL5304 data sheet rev. 0 | page 4 of 32 parameter test conditions/comments min typ max unit power supply vpos, vneg vpos 4.5 5.0 5.5 v quiescent current inum = iden = 10 a; vpos = 5 v, vneg = 0 v 13.5 16 ma 4.5 v vpos 5.5 v 10 17 ma vneg 6 nominal 0 v for single supply 0 ?5 v quiescent current inum = iden = 10 a; vpos = 5 v, vneg = 0 v ?8.5 ?7.3 ma vneg = ?5 v ?10.5 ?6 ma 1 slope is of the same magnitude but opposite sign for input applied to iden. 2 i z = i ref /10 (v ofs /v y ) . note that the error of i z is dependent on three parameters, i ref , v ofs , and v y . all three of those are trimmed. 3 output noise and small signal bandwidth are functions of input current; measured from the inum input to the vlog output. see t he section. typical performance characteristics 4 high-to-low currents (falling edge) repr esent the worst-case se ttling condition. low-to-high c urrents (rising edge) settling t imes are ~2 faster than the falling edge settling. settling time is measure d to 1 db error (10 mv/db; v log settles to within 10 mv of the final value). 5 iref applied to iden togethe r with 1p5v determin es the logarithmic intercept current, i z , and thereby the accuracy of the intercept. 6 using dual-supply operation with the vsmx, dcbi, and inps pins at ground, vneg needs to be in the ?2 v to ?5 v range for prope r device function.
data sheet ADL5304 rev. 0 | page 5 of 32 absolute maximum ratings table 2. parameter rating v pos +6 v v neg ?6 v input current to inum, iden 20 ma thermal data, 2-layer jedec board no air flow (exposed pad soldered to pcb) ja 61.6c/w jc 1.2c/w maximum power dissipation (exposed pad soldered to pc board) 0.6 w maximum junction temperature 125c operating temperature range ?40c to +85c storage temperature range ?65c to +150c lead temperature (soldering 60 sec) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ADL5304 data sheet rev. 0 | page 6 of 32 pin configuration and fu nction descriptions notes 1. nc = no connect. do not connect to this pin. 2. connect exposed p addle to vsm1 through vsm4 pins to provide low leakage guard. 09459-002 pin 1 indicator 1 nc 2 vsm1 3 vsm2 4 inum 5 iden 6 iref 7 vsm3 8 vsm4 24 inps 23 inms 22 vlog 21 scl1 20 scl2 19 scl3 18 acom 17 2vlt 9 vden 10 indn 11 comm 12 nmfs 13 vneg 14 dnfs 15 acom 16 hfcp 32 vnum 31 innm 30 imon 29 vpos 28 bsdc 27 dcbi 26 1p5v 25 nc ADL5304 top view (not to scale) figure 2. 32-lead lfcsp pin configuration table 3. pin function descriptions pin o. nemonic description 1, 25 nc no connect. do not connect to these pins. 2, 3, 7, 8 vsm1 to vsm4 guard pins for the inum and iden inputs. connect thes e pins to the 1p5v, dcbi, and inps pins for default single-supply setup; connect to ground if inum (photodiod e bias) is desired to be at ground (must have ?5 v < vneg < ?2 v). 4 inum numerator current input. 5 iden denominator current input. connect to the iref pin for most applications. 6 iref 100 na trimmed reference current output. connect to the iden pin for most applications. 9 vden voltage output of denominator log amplifier. connect this pin to the indn pin and decouple with an external 0.1 f capacitor to ground. 10 indn denominator voltage input to temperature compensation circuit. 11 comm main ground. 12 nmfs numerator speed bias (nomin al 1 k resistor to vneg pin). 13 vneg negative supply. 14 dnfs denominator speed bias (nominal 1 k resistor to vneg pin). 15, 18 acom analog common, low noise reference grou nd. important that both pins are always grounded. 16 hfcp high frequency compensation. 17 2vlt 2.0 v reference output. 19 scl3 7.5 k scaling resistor (see figure 1 ). default is nc. 20 scl2 5 k scaling resistor (see figure 1 ). default is to connect to the inms pin. 21 scl1 5 k scaling resistor (see figure 1 ). default is to connect to the vlog pin. 22 vlog primary logarithmic output. for i num = i den , the vlog pin is at the voltage applied to the inps pin. 23 inms output buffer amplifier inverting input. 24 inps output buffer amplifier noninverting input. the inps , dcbi, and vsm1 to vsm4 pins must be tied together. 26 1p5v 1.5 v reference output. connect to the inps, dcbi , and vsm1 to vsm4 pins for single-supply operation. 27 dcbi ~1.3 ma bias current. connect this pin to the vsm1 to vsm4 pins. see pin 2, pin 3, pin 7, and pin 8 description. 28 bsdc internal bias node. decouple with a series connection of 4 and 1 f to ground. 29 vpos positive supply. 30 imon photodiode monitor output. i mon = 1.1 i num . 31 innm numerator voltage input to temperature compensation circuit. 32 vnum voltage output of numerator log amplifier. connect this pin to the innm pin. for the fastest response, do not add an external capacitor. epad pad exposed paddle. connect the exposed paddle to the vsm1 to vsm4 pins to provide low leakage guard.
data sheet ADL5304 rev. 0 | page 7 of 32 typical performance characteristics v pos = 5 v, v neg = 0 v, t a = 25c; iden = iref; vsm1 to vsm4, 1p5v, dcbi, and inps tied together; scl1 = vlog; scl2 = inms; scl3 = open; scale = 200 mv/dec; vlog output load r l > 2 k, unless otherwise noted. 09459-003 3.0 2.5 2.0 1.5 1.0 0.5 0 1p 10p 100p 1n 10n 100n 1 10 100 1m 10m i num current (a) v log output (v) +85c +70c +25c 0c ?40c figure 3. v log vs. i num for multiple temperatures 09459-004 3.0 2.5 2.0 1.5 1.0 0.5 0 1p 10p 100p 1n 10n 100n 1 10 100 1m 10m i den current (a) v log output (v) +85c +70c +25c 0c ?40c figure 4. v log vs. i den for multiple temperatures; i num = 100 na 09459-005 3.0 3.5 2.5 2.0 1.5 1.0 0.5 0 1p 10p 100p 1n 10n 100n 1 10 100 1m 10m i num current (a) v log output (v) 100pa 1na 10na 100na 1a 10a 100a 1ma figure 5. v log vs. i num for multiple values of i den (decade steps from 100 pa to 1 ma) 09459-006 3 2 1 0 ?1 ?2 ?3 1p 10p 100p 1n 10n 100n 1 10 100 1m 10m i num current (a) error (db); 10mv/db +85c +70c +25c 0c ?40c figure 6. law conformance error vs. i num for multiple temperatures; normalized to 25c 09459-007 3 2 1 0 ?1 ?2 ?3 1p 10p 100p 1n 10n 100n 1 10 100 1m 10m i den current (a) error (db); 10mv/db +85c +70c +25c 0c ?40c figure 7. law conformance error vs. i den for multiple temperatures; i num = 100 na; normalized to 25c 09459-008 3 2 1 0 ?1 ?2 ?3 1p 10p 100p 1n 10n 100n 1 10 100 1m 10m i num current (a) error (db); 10mv/db 1ma 100a 10a 1a 100na 10na 1na 100pa figure 8. law conformance error vs. i num for multiple values of i den (decade steps from 100 pa to 1 ma)
ADL5304 data sheet rev. 0 | page 8 of 32 09459-009 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 1p 10p 100p 1n 10n 100n 1 10 100 1m 10m i den current (a) v log output (v) 1ma 100a 10a 1a 100na 10na 1na 100pa figure 9. v log vs. i den for multiple values of i num (decade steps from 100 pa to 1 ma) 09459-065 3.0 2.0 1.0 0 ?1.0 ?2.0 2.5 1.5 0.5 ?0.5 ?1.5 ?2.5 ?3.0 1p 10p 100p 1n 10n 100n 1 10 100 1m 10m i num (a) error (db); 10mv/db +3 ?3 figure 10. law conformance error distribution vs. i num (3 either side of mean) 09459-011 3.0 2.0 1.0 0 ?1.0 ?2.0 2.5 1.5 0.5 ?0.5 ?1.5 ?2.5 ?3.0 1p 10p 100p 1n 10n 100n 1 10 100 1m 10m i num (a) error (db); 10mv/db 3 70c 3 0c figure 11. law conformance error distribution vs. i num for 0c and 70c (3 either side of mean) 09459-010 3 2 1 0 ?1 ?2 ?3 1p 10p 100p 1n 10n 100n 1 10 100 1m 10m i den current (a) error (db); 10mv/db 1ma 100a 10a 1a 100na 10na 1na 100pa figure 12. law conformance error vs. i den for multiple values of i num (decade steps from 100 pa to 1 ma) 09459-013 3.0 2.0 1.0 0 ?1.0 ?2.0 2.5 1.5 0.5 ?0.5 ?1.5 ?2.5 ?3.0 1p 10p 100p 1n 10n 100n 1 10 100 1m 10m i num (a) error (db); 10mv/db 3 +85c 3 ?40c figure 13. law conformance error distribution vs. i num for ?40c and +85c (3 either side of mean) 09459-014 5 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 ?40 80 60 40 20 0 ?20 temperature (c) input offset (mv) +3 ?3 figure 14. (v inum ? v sum ) vs. i num for multiple temperatures
data sheet ADL5304 rev. 0 | page 9 of 32 09459-015 103 102 101 100 99 98 97 96 ?40 ?20 0 20 40 60 80 temperature (c) iref current (na) typical +3 ?3 figure 15. iref current vs. temperature 09459-016 5 4 3 2 1 0 ?1 ?2 ?3 ?4 ?5 ?40 ?20 0 20 40 60 80 temperature (c) 1p5v drift (mv) +3 ?3 figure 16. 1p5v drift vs. temperature 09459-017 1.515 1.510 1.505 1.500 1.495 1.490 ?5?4?3?2?1012345678910 load current (ma) reference voltage (v) figure 17. 1p5v vs. i load (positive current defined into 1p5v pin) 09459-018 i mon current (ma) count 0 50 100 150 200 250 300 1.00 1.05 1.10 1.15 1.20 figure 18. i mon histogram at i num = 1 ma 09459-019 5 4 3 2 1 0 ?1 ?2 ?3 ?4 ?5 ?40 ?20 0 20 40 60 80 temperature (c) 2vlt drift (mv) +3 ?3 figure 19. 2vlt drift vs. temperature 09459-020 2.000 1.995 1.990 1.985 1.980 1.975 1.970 ?20 ?15 ?10 ?5 0 load current (ma) reference voltage (v) figure 20. 2vlt vs. i load (positive current defined into 2vlt pin)
ADL5304 data sheet rev. 0 | page 10 of 32 09459-024 10 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 100 1k 10k 100k 1m 10m 100m frequency (hz) normalized response (db) 1ma 100a 10a 1a 100na 10na 1na figure 21. small signal ac response from i num to v log for i num in decade steps from 1 na to 1 ma, i den = 100 na 100 10 1 0.1 0.01 100 1k 10k 100k 1m spot noise (v rms/ hz) 09459-028 10m frequency (hz) step is analyzer artifact 100pa 1na 10na 100na 1a 10a 100a 1ma equip limit figure 22. spot noise spectral dens ity at vlog vs. frequency for i num in decade steps from 1 na to 1 ma (noise at lower frequencies, where nsd is flat, is limited by resistan ce used to generate dc i num current. see the noise vs. current section for further explanation.) 09459-026 2.7 2.5 2.3 2.1 1.9 1.7 1.5 1.3 1.1 0.9 0.7 0 102030405060 time (s) v log (v) 1ma to 10ma 100a to 1ma 10a to 100a 1a to 10a 100na to 1a 1na to 10na 10na to 100na figure 23. pulse response for i num in decade steps from 1 na to 1 ma, i den = 100 na 09459-027 100 1k 10k 100k 1m 10m 100m frequency (hz) normalized response (db) 10 5 0 ?5 ?10 ?15 ?20 ?25 1ma 100a 10a 1a 100na 10na figure 24. small signal ac response from i den to v log for i den in decade steps from 10 na to 1 ma; i num = 100 na 100 10 1 0.1 0.01 0.001 100p 1n 10n 100n 1 spot noise (v rms/ hz) 09459-029 10 100 1m i num (a) 100hz 1khz 10khz 100khz 1mhz 10mhz figure 25. spot noise spect ral density at vlog vs. i num in decade frequency steps from 100 hz to 10 mhz 09459-033 40 20 0 10 30 4 2 1 0 ?1 ?2 ?3 ?4 3 ?20 ?10 ?30 ?40 ?2024681012 time (s) v log output error (mv) error (db); 10mv/db 100na to 10na 1a to 100na 10a to 1a 100a to 10a 1ma to 100a input figure 26. normalized falling edge settling of i num to within 1 db (error = 10 mv/db)
data sheet ADL5304 rev. 0 | page 11 of 32 09459-030 2.3 2.1 1.9 1.7 1.5 1.3 1.1 0.9 0.7 0.5 0.3 0 102030405060 time (s) v log (v) 1ma to 10ma 100a to 1ma 10a to 100a 1a to 10a 100na to 1a 10na to 100na figure 27. pulse response for i den in decade steps from 1 na to 1 ma; i num = 100 na 09459-032 10 m 1m 100 10 1 100n 0 2 04 06 08 time (s) i mon current (a) 0 1.1a to 11a 11a to 110a 110a to 1.1ma figure 28. i mon pulse response vs. i num 09459-129 5 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 ?40 ?20 0 20 40 60 80 temperature (c) delta slope (mv/dec) +3 ?3 figure 29. slope drift vs. temperature for 200 mv/dec (3 to either side of mean) 09459-130 10 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 ?40 ?20 0 20 40 60 80 temperature (c) delta v log (mv) +3 ?3 figure 30. logarithmic offset drift vs. temperature (3 to either side of mean) 09459-131 inum v os (mv) count 0 50 100 150 200 250 ?1.0 ?0.5 0 0.5 1.0 figure 31. (v num ? v sum ) histogram at 25c 09459-132 1p5v voltage (v) count 0 50 100 150 200 250 1.496 1.498 1.500 1.502 1.504 figure 32. 1p5v histogram
ADL5304 data sheet rev. 0 | page 12 of 32 09459-133 2vlt voltage (v) count 0 50 100 150 200 300 250 1.996 1.998 2.000 2.002 2.004 figure 33. 2vlt histogram 09459-134 inum slope (mv/dec) count 0 50 100 150 200 300 250 195.0 197.5 200.0 202.5 205.0 figure 34. distribution of logarithmic slope (nominally 200 mv/dec) 09459-135 i ref current (na) count 0 140 120 100 80 60 40 20 95.0 105.0 97.5 100.0 102.5 figure 35. distribution of i ref (nominally 100 na) 09459-136 v offset (v) count 0 180 160 140 120 100 80 60 40 20 1.495 1.505 1.498 1.500 1.503 figure 36. distribution of v log for i num = i den = 100 na (nominally 1.500 v) 09459-137 temperature (c) supply current (ma) ?15 20 15 10 2 0 ?5 ?10 ?40 80 60 40 20 0 ?20 v pos single supply v neg single supply v pos dual supply v neg dual supply figure 37. supply current vs. temperature (|v pos |, |v vneg |)
data sheet ADL5304 rev. 0 | page 13 of 32 test circuits 09459-038 vsum vpos vneg 1p5v 2vlt agilent 34970a data acquisition unit ADL5304 2 30 3 4 5 6 8 7 monitor and pd bias (1.1 i num ) temperature compensation 1.5v 1.5v 32 31 26 9 imon vnum innm vden hfcp comm nmfs vneg dnfs v neg indn 1p5v 2vlt dcbi bsdc vsm1 vsm2 vsm3 iref iden inum vsm4 10 11 27 29 28 100na 1.5v 17 24 2v bias and v ref 12 13 14 acom 15 16 inps inms vlog 23 22 5k ? 5k ? 1k ? 1k ? 7.5k ? 21 20 19 18 scl1 scl2 scl3 acom vpos v num v den i log keithley 236 smu source current measure voltage keithley 236 smu source current measure voltage 0.1f 0.1f figure 38. setup for measuring logarithmic/slope/offset conformance hp3577b network analyzer output input r input a 09459-039 ADL5304 2 30 3 4 5 6 8 7 monitor and pd bias (1.1 i num ) temperature compensation 1.5v 1.5v 32 31 26 9 imon vnum innm vden hfcp comm nmfs vneg dnfs v neg indn 1p5v 2vlt dcbi bsdc vsm1 vsm2 vsm3 iref iden inum vsm4 10 11 27 29 28 100na 1.5v 17 24 2v bias and v ref 12 13 14 acom 15 16 inps inms vlog 23 22 5k? 5k? 1k ? 1k ? 7.5k ? 21 20 19 18 scl1 scl2 scl3 acom vpos v num v den i log 0.1f 0.1f ad8138 evaluation board modified to provide dc offset j1 j2 j3 j4 50 ? 50 ? hp11667b splitter input 1k? to 10m ? to set current 50? term figure 39. setup for measuring bandwidth
ADL5304 data sheet rev. 0 | page 14 of 32 agilent 33250a pulse generator pulse output trigger output lecroy sda6000 trigger input 50? ap1m 1m ? 09459-040 ADL5304 2 30 3 4 5 6 8 7 monitor and pd bias (1.1 i num ) temperature compensation 1.5v 1.5v 32 31 26 9 imon vnum innm vden hfcp comm nmfs vneg dnfs v neg indn 1p5v 2vlt dcbi bsdc vsm1 vsm2 vsm3 iref iden inum vsm4 10 11 27 29 28 100na 1.5v 17 24 2v bias and v ref 12 13 14 acom 15 16 inps inms vlog 23 22 5k? 5k? 1k ? 1k? 7.5k ? 21 20 19 18 scl1 scl2 scl3 acom vpos v num v den i log 0.1f 0.1f 1k? to 10m ? to set current 50? term hp11667b splitter input scope input figure 40. setup for measuring pulse settling agilent 33250a pulse generator pulse output trigger output bcp model 400 1300nm laser laser output modulation input jds fitel ha9 attenuator lecroy sda6000 trigger input scope input ap1m 1m ? 09459-041 ADL5304 2 30 3 4 5 6 8 7 monitor and pd bias (1.1 i num ) temperature compensation 1.5v 1.5v 32 31 26 9 imon vnum innm vden hfcp comm nmfs vneg dnfs v neg indn 1p5v 2vlt dcbi bsdc vsm1 vsm2 vsm3 iref iden inum vsm4 10 11 27 29 28 100na 1.5v 17 24 2v bias and v ref 12 13 14 acom 15 16 inps inms vlog 23 22 5k ? 5k ? 1k ? 1k ? 7.5k ? 21 20 19 18 scl1 scl2 scl3 acom vpos v num v den i log 0.1f 0.1f 100 ? 8/125m single mode fiber abb hafo 1a227 figure 41. setup for measuring photodiode pulse response
data sheet ADL5304 rev. 0 | page 15 of 32 09459-042 ADL5304 2 30 3 4 5 6 8 7 monitor and pd bias (1.1 i num ) temperature compensation 1.5v 1.5v 32 31 26 9 imon vnum innm vden hfcp comm nmfs vneg dnfs v neg indn 1p5v 2vlt dcbi bsdc vsm1 vsm2 vsm3 iref iden inum vsm4 10 11 27 29 28 100na 1.5v 17 24 2v bias and v ref 12 13 14 acom 15 16 inps inms vlog 23 22 5k ? 5k ? 1k ? 1k ? 7.5k ? 21 20 19 18 scl1 scl2 scl3 acom vpos v num v den i log keithley 236 smu source current measure voltage keithley 236 smu source current measure voltage 0.1f 0.1f figure 42. setup for measuring output agilent 33250a pulse generator pulse output trigger output lecroy sda6000 trigger input 50? ap1m 1m ? 09459-043 ADL5304 2 30 3 4 5 6 8 7 monitor and pd bias (1.1 i num ) temperature compensation 1.5v 1.5v 32 31 26 9 imon vnum innm vden hfcp comm nmfs vneg dnfs v neg indn 1p5v 2vlt dcbi bsdc vsm1 vsm2 vsm3 iref iden inum vsm4 10 11 27 29 28 100na 1.5v 17 24 2v bias and v ref 12 13 14 acom 15 16 inps inms vlog 23 22 5k? 5k? 1k ? 1k? 7.5k ? 21 20 19 18 scl1 scl2 scl3 acom vpos v num v den i log 0.1f 0.1f 1k ? to 10m ? to set current 50 ? term hp11667b splitter input scope input 1k ? to 100k ? load figure 43. setup for measuring imon pulse response
ADL5304 data sheet rev. 0 | page 16 of 32 terminology in the case of dual-supply operation of the device, the intercept can be shifted to different values depending on where the vsm1 to vsm4, dcbi, and inps pins are biased; the only recommended values are either 1.5 v via connection to the 1p5v pin, as in the case of single-supply operation, or ground when a dual supply is used. optical power optical power is defined as photon energy per unit of time measured as radiant flux () or radiant power, which is radiant energy (q) per unit time. photodiode responsivity photodiode (pd) responsivity, , is a constant that correlates optical power (p opt ) with pd current (i pd ). i pd = p opt (1) for example, if connected to ground, then the intercept is at i z = i den = i num for which log(i num /i den ) = 0. this is how most people interpret the function log(x). the most practical way to define intercept is to simply always use log 10 (i num /i den ) = 0 as the reference point. the only consequence is that a v ofs needs to be introduced depending on how the output buffer gain and offset is set up. where typical values for of ingaas p-intrinsic-n (pin) photo- diodes are in the range of 0.6 a/w to 1 a/w. in the case of 1 a/w, this means that for 1 mw of incident optical power, p opt , the pd delivers 1 ma of current, i pd . ofs den num y log v i i vv + ? ? ? ? ? ? ? ? = 10 log (3) when the photodiode current input to the ADL5304 is divided by the responsivity, the log slope directly represents the change in input optical power, p opt . for the default single-supply setup, as shown in figure 1 , v y = 0.2 v/decade and v ofs = 1.5 v (derived from the 1p5v pin), and i den is supplied by the on-chip trimmed i ref = 100 na. dark current all reverse-biased diodes develop a current due to the random generation of electrons/holes in the depletion region. in photo- diodes, this current occurs with no incident light falling on the diode and is called the dark current, i dk . dark current limits the minimum signal that can be reliably detected. for high speed ingaas pin photodiodes, the i dk is typically around 5 na. for a photodiode with a responsivity of 1 a/w, a 5 na i dk limits minimum measureable optical power to ?53 dbm. the relationship between i z and v ofs is as follows: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = = = 0.2v/dec 1.5v 10 na100 10 10 51 y vp y ofs v v ref v v den z i i i (4) logarithmic function the logarithmic function is ? ? ? ? ? ? ? ? = z num y log i i vv 10 log (2) because i ref and v y are trimmed for the default setup with v ofs = 1.500 v, i z should also be a stable quantity; however, because it is a calculated value determined by the i ref , v 1p5v , and v y parameters, its distribution is the combination of the three parameters and wider than the original parameters. the ideal single- and dual-supply ADL5304 responses are shown in figure 44 . 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?1.0 ?0.8 v log output voltage (v) 1p 10p 100p 1n 10n 100n 1 10 100 1m 10m i num input current (a) 09459-054 i num = i den single supply v sum = 1.5v dual supply v sum = 0v 200mv/dec 200mv/dec i num = i den logarithmic slope logarithmic slope is the change in output voltage (v log ) for a given change in input current usually shown as a semi-log graph where one input current (i num or i den ) is plotted on a log scale, and the output voltage (v log ) is plotted on a linear scale. the other input current is fixed. typically, slope is denoted as v y with units of mv/decade or mv/db. for the ADL5304 , in the default configuration, v y = 200 mv/decade (10 mv/db). logarithmic intercept logarithmic intercept, i z , is an extrapolated value representing the input current where v log = 0 v. in single-supply operation (the vsmx pins = dcbi = inps = 1p5v), v log is always positive, and when the ADL5304 is operating in the default configuration of i den = i ref = 100 na, the logarithmic intercept occurs at i num = 3.162 fa. figure 44. ideal transfer function
data sheet ADL5304 rev. 0 | page 17 of 32 theory of operation basic concepts the ADL5304 exploits the logarithmic relationship between base emitter voltage, v be , and the collector current, i c , of a bipolar junction transistor (see equation 5). this is the fundamental basis of the extended class of translinear circuits. a log amp based on this unique property of the bipolar transistor is called a translinear log amp to distinguish it from log amps designed for rf applications, which use different principles while having similar objectives. v be = v t log ( i c /i s ) (5) two scaling quantities appear in equation 5: the thermal voltage, v t = kt/q, and the saturation current, i s . the thermal voltage is of crucial importance in determining the logarithmic slope in a translinear log amp. v t has a process invariant value of 25.69 mv at t = 25c and varies in proportion to the absolute temperature (ptat). saturation current, unlike v t , is a process and device dependent parameter. saturation current is typically approximately 10 ?16 a at 25c, but exhibits enormous variation over temperature, by a factor of more than a billion. the temperature dependence of saturation current is compensated in the ADL5304 by using a second reference transistor, having an identical variation, to stabilize the intercept by using the difference between the two v be s. input currents, i num and i den , are the numerator and denominator of the logarithmic argument that follows: v be = v t log ( i num / i den ) (6) in log ratio applications, both i num and i den may each vary over the full specified range of 1 pa to 10 ma. however, in default operation, i den takes the internally preset current of i ref = 100 na. equation 6 shows that the v be is still ptat, but the required logarithmic slope must be temperature stable; therefore, this is corrected using proprietary circuit techniques. using this correction the relationship between a photodiode current, i pd , applied to inum, and the voltage appearing at the output at vlog is v log = v y log 10 ( i pd /i z ) (7) where: v y is the log slope voltage (and, for the case of base-10 logarithms, it is also the volts per decade ). i z is the extrapolated log intercept. the relationship between v y and v be is a factor close to 3.333 in the default configuration from (v num ? v den ) to the output of vlog. because a decade change in the input current ratio results in close to a 60 mv/decade change in v be ; multiplying this by 3.333 results in 0.2 v/decade. during fabrication, v y is trimmed to 0.2 v/decade (10 mv/db), i ref to 100 na, v ofs to 1.500 v, and i z to 3.162 fa. when i pd = 1 pa, the output v log has a value of 0.5 v (see figure 44 ). i z is small because v log is always above ground potential even at the lowest end of the dynamic range, when using v ofs = 1.500 v. if a negative supply is used, this voltage can cross zero at the intercept value. the output for the value of i pd can be calculated using equation 8. for example, with an input current of 100 na, v log = 0.2 v log 10 (100 na/3.162 fa) = 1.500 v (8) the slope and intercept can be adjusted to suit the application, to either higher or lower values, without significant loss of calibration accuracy. optical measurements it is important to understand the transducer aspects of a photo- diode when interpreting the photodiode current relative to the incident optical power. in purely electrical circuits, current applied to a resistive load results in a power proportional to the square of the current. for a photodiode interface, however, there is a difference in scaling because photon-generated photodiode current (i pd ) flows in an element biased at a fixed voltage. i pd is equal to the optical power (p opt ) absorbed in the detector times the responsivity of the photodiode (). i pd = p opt (9) a similar relationship exists between the intercept current, i z , and effective intercept power, p z . i z = p z (10) therefore, the v out equation for the ADL5304 may be written as v log = v y log 10 ( p opt /p z ) (11) for the ADL5304 operating in its default mode, an i z of 3.162 fa corresponds to a p z of 3.95 fw for a diode having a responsivity of 0.8 a/w. an optical power of 12.5 w therefore generates v log = 0.2 v log 10 (12.5 w/3.95 fw) = 1.900 v (12) in optical applications, the interpretation of v log is as an equivalent optical power; therefore, the slope for calculation purposes remains 10 mv/db (for either current or power).
ADL5304 data sheet rev. 0 | page 18 of 32 decibel scaling when signal power is expressed in decibels above a reference level (for example, dbm, when the reference is 1 mw), logarithmic conversion has already been implicitly performed. therefore, the log ratio in the previous expressions becomes a simple difference. be careful in assigning variable names, because p is often used to denote actual power as well as this same power expressed in decibels. these are very different quantities. misunderstandings can be avoided by using d to denote decibel powers. when v y (the volts/decade ) is converted to its decibel value, = v y /10 (because there are 10 db per decade in the context of a power measurement), it can be written y v v log = 20 mv( d opt ? d z ) (13) where: d opt is the optical power expressed in decibels above a reference level. d z denotes the equivalent intercept power relative to the same level. using the previous example and assuming a reference power of 1 mw, a p opt of 12.5 w corresponds to a d opt of 10 log 10 (12.5 w/1 mw) = ?19.03 dbm; the equivalent intercept power of 3.95 fw corresponds to a d z of ?114.03 dbm. therefore, v log = 20 mv{ ?19.03 ? (?114.03) } = 1.900 v (14) the same result calculated with equation 12. circuit description the ADL5304 addresses a wide variety of interfacing conditions to meet the needs of fiber optic supervisory systems, as well as many nonoptical applications. this section explains the general structure of this log amp. the ADL5304 is an order of magnitude faster than any previous log amp that analog devices, inc., has made, through careful fet amp design; the key limitation in the speed at low currents. figure 45 is a simplified schematic of the front-end section of the ADL5304 . the numerator current, i num , is received at the inum pin. the voltage at this node is equal to that on the two adjacent guard pins, vsm2 and iden, differing only by the offset voltage of the jfet op amp that supports the operation of the translinear device q1 that converts the i num current to a logarithmic voltage. vsm2 is needed to provide the collector- emitter bias for q1, and it is preset to 1.5 v via the external connection to pin 1p5v. 09459-055 monitor and pd bias (1.1 i num ) 2 3 4 5 6 8 7 30 31 26 vsm1 vsm2 r mntr 32 vsm4 vsm3 iref iden inum 100na q2 q1 q3 1.5v 1.5v 10 9 vden indn vnum imon innm 1p5v 1.5v vref temp comp v num i log v den shield shield pd figure 45. simplified front-end schematic in conventional translinear log amps, the collector and base of q1 are both held at ground potential, this is not possible in a single-supply part. a second transistor, q2, operates at a collector current of i den . in most applications, this is the reference of i ref = 100 na, supplied internally and laser trimmed. the difference between the two v be s with q1 accepting a photodiode current of i num = i pd is v be1 ? v be2 = v t log 10 ( i pd / i ref ) (15) by adding an accurate ptat voltage of magnitude, v ofs = v t log 10 ( i ref / i z ) = 1.500 v (16) resulting in v be1 ? v be2 + v ofs = v t [log 10 ( i pd / i ref ) + log 10 ( i ref / i z )] = (kt/q) log 10 ( i pd / i z ) (17) the temperature variation of kt/q is then eliminated by an analog divider that essentially puts a variable proportional to temperature underneath the t in equation 17 and raising the magnitude of kt/q to a stable value of 0.2 v. therefore, for photodiode applications, v log = 0.2 v log 10 ( i pd / i z ) (18) when the vsm1to vsm4, dcbi, and inps pins are tied to ground and v neg < ?2 v, the offset (v ofs ) is removed, leaving the more general form. v log = 0.2 v log 10 ( i num / i den ) (19)
data sheet ADL5304 rev. 0 | page 19 of 32 bandwidth vs. current assuming a 20 khz net system bandwidth at this current, the integrated noise voltage is 70 v rms. the theoretical noise of v be vs. i c is shown in figure 46 . however, the log scaling of the v be is ~3 mv/db, and in the ADL5304 , this is increased to a slope of 10 mv/db at the vlog pin. therefore, the noise at vlog, predicted by equation 22, is multiplied by a factor of 3.33. secondary sources of noise, mostly in the analog divider used for temperature stabilization of the slope and the input fet buffer amplifiers, add to this ba sic noise. the measured data are shown in figure 22 . both the response time and wideband noise of translinear log amps are functions of the transistor collector current, i c , and only slightly amenable to improvement by circuit design. the bandwidth falls at low values of i c due to the effects of junction capacitances in q1 and the decrease in transconductance (g m ) of a bipolar transistor, which is a linear function of i c , or in the case of a photodiode application, the photocurrent, i pd . the corresponding incremental emitter resistance is r e = 1/ g m = v t / i pd = kt/ qi pd (20) note how at low frequencies the nsd flattens for input currents less than 10 na, this noise is limited by the resistor that makes the dc current. a 10 m resistor was used for these three currents with a dc bias voltage across the resistor of 1 mv, 10 mv, and 100 mv, respectively. and becomes extremely high at low currents (260 m at i c = 100 pa). therefore, even minute capacitances associated with the transistor can generate very long time constants. if the net effect of these capacitances is represented loosely as c j , the corresponding low-pass corner frequency is a 10 m resistor makes a noise current of 40.7 fa/ hz, which is converted via the g m of the logging transistor into a noise voltage. this voltage adds to the noise voltage of the bipolar transistor itself, as shown in figure 46 . the r e of the transistor is 1/g m and equal to 25.85 m at i c equals 1 na. together with the noise current of the source resistor, this makes a noise voltage at the emitter of the logging transistor (vnum) of 1.05 v/ hz; this contrasts with the noise voltage of the transistor itself of 0.46 v/ hz (~0.5 v/ hz). the total combined noise is ~1.15 v/ hz. f ?3db = qi pd /2 ktc j (21) showing the proportionality of bandwidth to current. using a value of 0.3 pf for c j , this becomes 20 mhz/a. the small signal bandwidth at i pd = 100 pa is thus only 2 khz. however, whereas this simple model can be useful in making the basic point, it excludes many other effects that limit its accuracy. at high currents, the subsequent signal processing limits the maximum overall bandwidth. noise vs. current the effect of the 10 m resistor at 100 pa of dc current becomes even more pronounced because the noise at vnum due to the source resistor is 10.5 v/ hz, whereas the transistor only contributes 1.46 v/ hz for a total of 10.6 v/ hz. for an ideal bipolar transistor, the voltage noise spectral density, s nsd , referred to v be , and caused by shot-noise mechanisms, evaluates to therefore, unless the resistor that makes the dc current becomes very large, in general, measurement at the lower currents is limited by the noise of the source resistor. this problem does not exist when using a photodiode because the resistance of the photodiode increases at the same rate as the logging transistor (see figure 47 ). s nsd = 14.6/ i c nv/hz ( t a = 27c) (22) where i c is in a. for example, at an i c of 1 na, s nsd evaluates to approximately 0.5 v/hz. 10 v 1v 100nv 10nv 1nv 100pv 100p 1n 10n 100n 1 10 100 1m 10m noise spectral density (v/ hz) i c (a) 09459-056 noise spectral density of v be figure 46. noise spectral density of v be vs. i c
ADL5304 data sheet rev. 0 | page 20 of 32 09459-047 r&s fsea30 spectrum analyzer input coax shield biased to vlog dc level 20mhz to 3.5ghz ADL5304 2 30 3 4 5 6 8 7 monitor and pd bias (1.1 i num ) temperature compensation 1.5v 1.5v 32 31 26 9 imon vnum innm vden hfcp comm nmfs vneg dnfs v neg indn 1p5v 2vlt dcbi bsdc vsm1 vsm2 vsm3 iref iden inum vsm4 10 11 27 29 28 100na 1.5v 17 24 2v bias and v ref 12 13 14 acom 15 16 inps inms vlog 23 22 5k ? 5k? 1k ? 1k ? 7.5k ? 21 20 19 18 scl1 scl2 scl3 acom vpos v num v den i log 0.1f 0.1f shield bias coax shield broken dut 5v 10k ? linear 15 turn 4k ? metal film ad8597 buffer +9v buffer ?9v 1m ? log conductive plastic dut 5v shielded enclosure dut 5v buffer +9v + 9v ? buffer ?9v ? 9v + + 9v ? 7805 shield bias 1k ? linear 15 turn figure 47. setup for measuring noise for i num = 100 pa, i num = 1 na, and i num = 10 na filtering to improve noise and dynamic behavior the noise at the output of a log amp, particularly at low current levels, leads to uncertainty in the measurement. noise amplitude is limited by the finite bandwidth. if measurement speed is not of primary concern, additional filtering can reduce noise. figure 48 shows the recommended locations for additional external filtering. note the ADL5304 consists of a current-to-voltage (transimpedance) conversion (i num or i den to v num ? v den ), followed by a voltage-to-current conversion (v num ? v den to i log ), and then followed by another current-to-voltage conversion (i log to v log ). typically, capacitors are not used on the numerator side (i num ) to keep the speed of the device as high as possible. on the denominator side (i den ), additional filtering is useful to reduce noise. in applications where i num is used as the reference to the logarithmic equation and i den is a variable, for example, where a reverse logarithmic slope is desired, filtering can be done on the numerator side (i num ). 09459-057 2 3 4 5 6 8 7 monitor and pd bias (1.1 i num ) temperature compensation 1.5v 1.5v 32 31 26 9 vnum innm vden indn 1p5v dcbi vsm1 vsm2 vsm3 iref iden inum vsm4 c1d c1n 10 27 100na 1.5v 24 bias inps inms vlog 23 22 5k ? 5k? 7.5k ? 21 20 19 18 scl1 scl2 scl3 acom v num v den c2d c3d c2n c3n cfb rn i log rd figure 48. possible external filtering locations
data sheet ADL5304 rev. 0 | page 21 of 32 capacitor, c1d, effectively reduces the bandwidth of the denominator input stage. a few picofarads of capacitance (<5 pf) reduce the bandwidth significantly for currents below approximately 1 a, though whereas 1 nf to 10 nf are normally enough to reduce the bandwidth up to the maximum 10 ma of input current. when measurement speed is of primary importance, it is better to add filtering after the fet amp outputs, in which case, c2d, rd, and c3d are the best locations. the resistor in this case should not be much larger than 1 k because there is a bias current that is approximately 35 a that flows from the temperature compensation block into each of the vden and vnum pins. inserting a resistor, as shown in figure 48 , lifts up the voltages at the innm and/or indn pins and potentially causes headroom problems in the temperature compensation block. when i den is used as the reference, as is normally done, then it is recommended that c1d is zero, c2d is a 0.1 f ceramic decoupling capacitor, rd is a short, and c3d is not placed. adding a capacitor, cfb, adds additional filtering at the buffer output. this capacitor also helps to optimize the pulse response by placing a zero across the feedback resistor (2.5 k in the default configuration). a good value to start with is 22 pf, this introduces a zero at 2.9 mhz that can improve the pulse responses for input currents above approximately 100 a. photodiode bias the ADL5304 provides for adaptive photodiode bias. a monitoring transistor, q3, connected in parallel with q1 (see figure 49 ), samples 1/10 th the input current, i num . this sampled current is multiplied by a factor of 11 to give an effective output current at the imon pin of 1.1 times i num . because the photodiode produces i num , the additional current has to flow in an external resistor, r mntr , equal to 10 r s , where r s is the value of the internal parasitic series resistance of the photodiode. this ensures that the actual junction of the photodiode is biased as close as possible to 0 v to minimize dark current. capacitor, cmon, provides potential filtering and dynamic currents during fast transients. the value for best bias response depends on the photodiode used and should be determined experimentally. nominally, cmon = 0. if the adaptive bias is not used, the imon pin must be connected to ground. it is easy to provide a 0.5 v reverse bias across the diode by using the 2vlt reference and connecting it to the cathode. because the ADL5304 forces the voltage at inum very close to 1.500 v, the trimmed 2.000 v ensures a precise 0.5 v reverse bias for the pd. 09459-058 monitor and pd bias (1.1 i num ) 2 3 4 5 6 8 7 30 vsm2 vsm1 r mntr 32 vsm3 vsm4 iref iden inum 100na q2 q1 q3 1.5v 1.5v 9 vden vnum imon shield shield pd cmon from 1.5v vref figure 49. adaptive photodiode bias one example of dual-supply operation is shown in figure 50 , where the 2.000 v (the 2vlt pin) reference ensures a precisely controlled, reverse bias across the pd. the user can use other reverse bias voltages but needs to provide them separately. note that when the vsmx pins are grounded, the dcbi and inps pins must also be grounded. 09459-150 monitor and pd bias (1.1 i num ) 2 3 4 5 6 8 7 30 vsm2 vsm1 32 vsm3 vsm4 iref iden inum 100na q2 q1 q3 9 vden v num imon shield shield pd from 2.0v v ref figure 50. pd bias with v sum at ground and using 2.000 v
ADL5304 data sheet rev. 0 | page 22 of 32 09459-060 temperature compensation 26 1p5v dcbi 27 1.5v 24 bias inps inms vlog 23 22 5k? 5k? 7.5k ? 21 20 19 15 scl1 scl2 scl3 i log acom reference outputs the ADL5304 has three trimmed precision references, two voltages, and one current (i ref ). the voltages are 1.500 v and 2.000 v at the 1p5v and 2vlt pins, respectively. the 1p5v reference is intended to provide the bias to the vsm1 to vsm4, dcbi, and inps pins; it can sink up to 10 ma and source a maximum of about 5 ma. the 2vlt reference can source up to 20 ma of current, but it cannot sink any current. the primary use of the 2.0 v reference is for photodiode bias, or to generate reference currents other than the 100 na provided by i ref . together with a precision resistor, the 1.5 v and 2.0 v references can reliably generate any current up to approximately 5 ma. the i ref current, nominally 100 na, flows out of the iref pin and is primarily used as an input to the iden pin to provide the denominator current, i den . the choice of 100 na places it in the middle of the 1 pa to 10 ma range. i ref can also be used as the input to the inum pin and thereby invert the basic log response of the ADL5304 . if i den = i ref , v log increases with increasing i num . whereas if i num = i ref and the input current is applied to iden, v log decreases with increasing i den . figure 51. buffer amplifier in default configuration the buffer amplifier is a voltage feedback op amp with supplies between vpos and vneg. for single-supply operation, the vneg pin is tied to ground, and the inps pin, the positive input of the op amp, to the 1p5v pin. if a ground referenced input is desired at the inum or iden pins, then the inps and dcbi pins together with the vsmx pins must be tied to ground, and vneg needs to be less than ?2 v. if larger slopes are required, vpos can increase to +5 v, and vneg can increase to ?5 v. for example, if the scl3 pin is connected to vlog, and scl1 and scl2 remain open, the internal 7.5 k resistor, together with the 80 a/decade i log , provides a slope of 0.6 v/decade at the vlog pin. implementation of slopes of 0.2 v/decade to 0.8 v/decade is easily accomplished. buffer amplifier a buffer amplifier completes the signal chain that takes the i log current from the temperature compensation block and converts it to a voltage at the vlog pin. the buffer amplifier gain and offset can be configured to provide different logarithmic slope and intercept at the v log output. on-chip resistors provide optimized scale factors and intercepts via the scl1, scl2, and scl3 pins. for example, in figure 51 , the default setup provides a scale of 0.2 v/decade and an intercept of 3.162 fa. v ofs = v log = 1.5 v when the internal i log = 0 a, which corresponds to i num = i den . i log varies from ?400 a to +400 a with a scale of 80 a/decade over the full 200 db input current range. in the default configuration, i log is negative for i num > i den and positive for i num < i den . if the input current is applied to the iden pin and the reference current (i ref ) to the inum pin, the slope of v log is negative and the range is inverted, that is, v log is 2.5 v for i den = 1 pa, and v log is 0.5 v for i den = 10 ma. setting the log slope and intercept the choice of optimal slope and intercept depends on the application and supply voltage(s). for example, when an input current range of less than the full 200 db is desired, a higher slope can be chosen to better use the full voltage span available at vlog, and perhaps optimally position it to suit the input capacity of a subsequent analog-to-digital converter (adc). very high slopes, such as 0.8 v/decade, can be realized, allowing a smaller range of i pd to be measured at high sensitivity. any other intercept and slope can be realized using external resistors, but these do not, in general, form accurate ratios to the on-chip resistors. therefore, some inaccuracies should be expected. if the scl1, scl2, and scl3 pins are not connected and a resistor is placed between the inms and vlog pins, the i log current is forced through the external resistor and thereby has a log slope that is 80 a/decade times r ext ; v ofs is equal to the voltage applied to the inps pin.
data sheet ADL5304 rev. 0 | page 23 of 32 table 4. vlog scaling options option pin scl1 pin scl2 pin scl3 pin inps pin inms v y (v/dec) i z (a) v ofs (v) single-supply operation (vneg = 0 v; vsmx = dcbi = inps = 1p5v) 1 1 vlog inms open 1p5v scl2 0.2 3.16 f 1.5 2 vlog inms vlog 1p5v scl2 0.15 0.01 f 1.5 3 vlog inms ground 1p5v scl2 0.2 0.01 f 2.0 4 vlog open ground 1p5v open 0.4 56.2 f 2.5 5 vlog open open 1p5v open 0.4 17.8 p 1.5 6 open open vlog 1p5v open 0.6 316 p 1.5 7 open vlog open 1p5v open 0.8 1.33 n 1.5 8 vlog inms 2vlt 1p5v scl2 0.2 21.6 f 1.333 dual-supply operation (vneg < ?2 v; vsmx = dcbi = inps = ground) 9 2 vlog inms open ground scl2 0.2 100 n 0 10 vlog inms vlog ground scl2 0.15 100 n 0 11 vlog open open ground open 0.4 100 n 0 12 open open vlog ground open 0.6 100 n 0 13 open vlog open ground open 0.8 100 n 0 1 default setup for single supply and vsmx = 1.5 v. 2 default setup for dual supply and vsmx = ground. the default setups are noted in table 4 . other intercepts are achieved by injecting different currents into the iden pin, for example, if i den = 1 a, as shown in figure 52 , the vlog transfer function is simply shifted by one decade to the right. one way of doing this is to put a precision 500 k resistor between the 2vlt and iden pins in the single- supply default setup. the intercept is moved up to 31.62 fa, and all output voltages for a given i num are lowered by one decade, that is, by 0.2 v at v log . for example, the new i den = 1 a, and v log = 1.3 v for i num = 100 na. this is particularly useful if the slope is already as desired but the desired intercept cannot be achieved with the on-chip resistors. only a shift toward the right makes sense because a shift to the left requires excessively large resistors. 09459-061 monitor and pd bias (1.1 i num ) 2 3 4 5 6 8 7 30 17 31 26 vsm1 vsm2 r mntr 32 vsm4 vsm3 iref iden inum 100na q2 q1 q3 1.5v 1.5v 10 9 vden indn imon 2vlt innm 1p5v 1.5v vref temp comp v num i log v den shield shield pd 500k ? vnum figure 52. intercept shifted one de cade right via external resistor, reference current i den = 1 a slope inversion table 4 lists only those slopes that are positive because this is the expected normal operation in measurement mode. the slopes can be inverted by two methods. by using i num = i ref = 100 na, in which case, the intercepts, i z , are at larger currents mirrored from the values shown in table 4 around the 100 na reference current. for example, for the default setup with v y = 0.2 v/decade and i z = 3.162 fa, swapping inum and iden connections result in v y = ?0.2 v/decade and i z = 3.162 a. the second method is to simply swap the connections between the vnum and vden pins and the inputs to the temperature compensation cell (innm and indn), as shown in figure 53 (compare to figure 52 ). this technique is particularly useful if both negative log slope and adaptive photodiode biasing via i mon are desired together. 09459-062 monitor and pd bias (1.1 i num ) 2 3 4 5 6 8 30 31 vsm1 vsm2 vsm4 vsm3 r mntr 32 iref iden inum 100na q2 q1 q3 10 9 vden indn imon vnum innm temp comp v num v den shield shield pd from 1.5v vref 7 figure 53. simple slope inversion method
ADL5304 data sheet rev. 0 | page 24 of 32 log ratio operation because the ADL5304 has two equal inputs, i num and i den , log ratio operation is possible. the only difference between i num and i den is that the i mon current derives from the i num signal and allows adaptive photodiode bias at this input only. assuming that the ratio i num /i den can, in general, be either greater or less than unity, v log can be of either polarity, requiring a negative supply in some cases. the value of v log depends on the minimum ratio and the slope chosen for the application. for example, if the ratio can vary from 1:1000 to 1000:1 and a slope of 20 mv/db is required, the peak swing is 1.2 v around v ofs . option 5 in table 4 provides this with an intercept i z of 17.8 pa (v ofs = 1.5 v) with v log = 1.2 v around v ofs = 1.5 v, which results in 0.3 v v log 2.7 v.
data sheet ADL5304 rev. 0 | page 25 of 32 applications information using the ADL5304 the basic connections for single-supply operation are shown in figure 55 . supply decoupling is not critical and the suggested values are conservative; however, it is recommended that a ferrite bead be placed in the supply lines together with a 0.1 f decoupling capacitor. ferrite beads are preferable to resistors because they do not produce a dc voltage drop that can affect reference levels. in figure 55 , the slope is 10 mv/db or 0.2 v/decade, and the intercept is 3.162 fa. for the full dynamic range of 200 db (100 db optical), v log varies from 0.5 v to 2.5 v (see small diagram at the output in figure 55 ) with v log = v ofs = 1.5 v, when i num = i den . because the iden pin is connected to the iref pin, i den = 100 na. figure 55 also shows the setup for the adaptive photodiode bias. if this is not desired, ground the imon pin, remove r mntr , and provide the desired bias voltage greater than 1.5 v to the cathode of the pd. as noted in the photodiode bias section, the on-chip 2 v reference can be used for this purpose and provides an exact 0.5 v reverse bias together with the 1.5 v that is forced by the fet amp to the anode via the inum pin. using the adaptive bias the positive bias on the photodiode cathode must be adequate to support the peak current, which is limited by its internal series resistance, r s . typical values of r s are 5 . a model of a repre- sentative photodiode (jdsu epm 605) is shown in figure 54 . 09459-063 pd 2 case 1 1nh 1.5nh r s 0.55pf 0.5pf 0.5pf 0.13pf 5nh 5nh figure 54. photodiode model it is desirable to use a small bias at very low levels of illumination to minimize the error due to current leakage across the diode terminals. the adaptive bias achieves this automatically even for larger currents through the addition of the external resistor, r mntr , that is 10 times r s . in case of uncertainty in r s , an r mntr that is slightly greater than 10 times r s is recommended. in the limit, when r mntr is not present at all, the voltage at the imon pin increases until the current source saturates and absorbs the excess 10% of current that the imon output generates. however, this defeats the purpose of the adaptive bias; therefore, users must ensure that r mntr is present when using the adaptive bias. ADL5304 09459-064 2 30 3 4 5 8 7 monitor and pd bias (1.1 i num ) temperature compensation 32 31 26 9 imon vnum innm vden acom comm indn 1p5v 2vlt dcbi vpos bsdc vsm1 1.5v vsm2 1.5v iref iden inum vsm3 1.5v vsm4 1.5v 10 11 27 29 100na 1.5v 17 24 2v bias and v ref 15 14 inps inms vlog 23 22 5k ? 5k ? 7.5k ? 21 20 19 18 scl1 scl2 scl3 acom r mntr 6 pd shield shield 0.1f 0.1f 0.1f 0.1f hfcp 16 0.1f 1f 28 4.02 ? v num v den important: ~1ma bias current flows out of dcbi. needs to be connected to 1p5v. fb v pos i log r load 2.5v 1.5v 0.5v 1p 100n 10m nmfs vneg dnfs 12 13 r nmfs r dnfs figure 55. basic connections for single-supply operation
ADL5304 data sheet rev. 0 | page 26 of 32 summing node voltage it is important to reiterate that the vsm1 to vsm4, dcbi, and inps pins always need to be tied together. failure to do so results in erroneous outputs at vlog. the vsmx pins must be well decoupled to provide a good ac ground. leakage vsm2 and vsm3 are critical nodes because they are used by the fet amplifiers to define the voltages on the inum and iden pins. furthermore, the voltage applied to vsm2 and vsm3 is also used to drive the shield around the inputs, which becomes critical at low currents (<1 na) to minimize leakage. a voltage difference between the inum and vsm2 pins of 1 mv together with a leakage resistor of 100 m results in a current of 10 pa. if the current flows into the device, this leakage current limits the lowest measurable input current. even worse, if the current is negative (that is, pulls current out of the input pin), the input voltage pulls low, and the fet amp output rails positive. this can happen rather easily when the input is biased at 1.5 v. for example, a 1 g resistor between the input pin and ground generates a 1.5 na current that flows from the input pin to ground and thereby pulls the input nodes low. a log amp input is unidirectional, and it can accept current in only one direction. a current that flows in the wrong direction breaks the loop that biases the inputs. for this reason, if currents of less than about 1 na are to be measured, it is critical that a guard be used, and that the boards are cleaned of any contaminants including solder flux. in the case where the leakage is so large that it cannot be overcome by the input current, the v log output rails to the negative or positive ends of the output range, depending on whether it is inum or iden that has the leakage. vlog output the vlog output is somewhat sensitive to loading and does not like to drive large capacitances or very small resistors, for this reason, it is recommended to keep c load < 5 pf and r load > 10 k. dynamic response the ADL5304 does not require input compensation networks to stabilize the circuit. however, a negative going current can happen during normal dynamic operation, for example, during current steps that decreases from larger to smaller values. during a large step, the input loop can temporarily open causing a transient invalid v log output. loop recovery time is directly related to the input current; therefore, the smaller the input current, the longer it takes for the ADL5304 to recover. careful design that reduces parasitic capacitance at the inum and iden inputs helps to reduce this recovery time; however, this behavior cannot be eliminated because it is characteristic of translinear log amps. some pulse response measurement results with an actual photo- diode (1a227, 0.8 a/w, 0.7 pf) are shown in figure 56 and figure 57 for the setup in figure 55 . 09459-035 2.3 1.9 1.5 1.7 2.1 0.9 1.1 1.3 0.7 0.5 0 20 40 60 80 100 time (s) v log output (v) laser limit 1a 100na 10na 1na 100pa 10pa figure 56. photodiode response for input currents of approximately 10 pa to >1 a where laser limit encountered 09459-034 1.3 1.1 0.9 0.7 0.5 0.3 02468 time (ms) v log output (v) 1 0 100pa 10pa 1pa figure 57. increased time scale to show measurements down to i num ~ 1 pa (~1.25 pw; ?89.03 dbm) using a negative suppl in most applications of the ADL5304 , a single supply is adequate. a single supply also provides the lowest power operation. dual supplies are needed if the user wants to bias the anode of the photodiode at ground, as was shown in figure 50 . the negative supply needs to absorb the device bias current, the load current of the buffer, and the maximum input currents. with the summing node moved to ground, the ADL5304 can be used as a voltage-input log amp, using a suitably scaled resistor from the voltage source to the inum pin. the logarithmic accuracy for small voltages is limited by the offset of the jfet op amp, appearing between this pin and vsum. the iden pin can likewise be driven from a voltage signal. when very large input currents (inum or iden greater than ~5 ma) and very low temperatures (?40c) are expected, use a negative voltage on vneg.
data sheet ADL5304 rev. 0 | page 27 of 32 evaluation board schematic and silkscreens 09459-202 figure 58. evaluation board schematic
ADL5304 data sheet rev. 0 | page 28 of 32 09459-200 figure 59. evaluation board, primary side 09459-201 figure 60. evaluation board, secondary side
data sheet ADL5304 rev. 0 | page 29 of 32 outline dimensions 032807-a compliant to jedec standards mo-220-vhhd-2 1 32 8 9 25 24 17 16 2.85 2.70 sq 2.55 top view coplanarity 0.08 3.50 ref 0.50 bsc pin 1 indicator 0.60 max 0.60 max 0.20 min exposed pad (bottom view) pin 1 indicator 0.30 0.25 0.18 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 0.05 max 0.02 nom seating plane 0.50 0.40 0.30 5.00 bsc sq 4.75 bsc sq for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 61. 32-lead lead frame chip scale package [lfcsp_vq] 5 mm 5 mm body, very thin quad (cp-32-8) dimensions shown in millimeters ordering guide model 1 temperature range package description ordering quantity package option ADL5304acpz-r2 ?40c to +85c 32-lead lfcsp_vq 250 cp-32-8 ADL5304acpz-r7 ?40c to +85c 32-lead lfcsp_vq, 7 tape and reel 1500 cp-32-8 ADL5304acpz-rl ?40c to +85c 32-lead lfcsp_vq, 13 tape and reel 5000 cp-32-8 ADL5304-evalz evaluation board 1 z = rohs compliant part.
ADL5304 data sheet rev. 0 | page 30 of 32 notes
data sheet ADL5304 rev. 0 | page 31 of 32 notes
ADL5304 data sheet rev. 0 | page 32 of 32 notes ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d09459-0-9/11(0)


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